XILINX FPGAのBlock RAMをROMとして使う方法 (FPGAに内蔵のBLOCK-RAMにROMとして初期値を与える方法)

FPGAに内蔵のBLOCK-RAMにROMとして初期値を与える方法の質問が多いので作成しました。

ROMとして使う場合の初期値の与え方ですが、下記の方法があります。
・HDL記述1:普通のHDLの構文で書いてROMをインスタンシェートする
・HDL記述2:synthesis attributeを使う(XILINX独自)
・UCF記述:UCFファイル(User Constraints File)にINITを使う(XILINX独自)
・埋め込み: DATA2BRAM ツールでbitファイルに混合埋め込み(XILINX独自)

理想を言えばHDL記述1の方法を用いればXILINX/ALTERA/他とソースリストを共通にする事ができます。

しかし、ここでは確実に結果が得られるHDL記述2の方法について書きます。

ちなみにALTERAの場合はHEXファイルやMIFファイル(Memory Initialization File)での初期値の指定が可能です。
ALTERAの場合はBLOCK-RAM(lpm_ram_dp)を使用する場合はMegaFunction Wizardを用いて生成する事を強く推奨しています。
(手作業でパラメータ設定が不十分で入力したものだと変な動きをするものを生成するらしい)

・ ALTERA RAM Megafunction User Guide

・ブロック SelectRAM をインスタンシエートおよび初期化する方法

・ RAMB4_S8を使った場合(512アドレスx8bit幅=4096bits)

・ Block Select RAM 機能の使い方(XAPP130)

・ RAMB4_Sn 4096-Bit Single-Port Synchronous BlockRAM

Spartan-II
Spartan-IIE
Spartan-3
Virtex
Virtex-E
Virtex-II
Virtex-II Pro
等で使用できます。

・ "rom.v"で保存

//
//  XILINX,Spartan-2 Block Select RAM
//  BLOCK-RAMをROMとして使う方法
//
//  ISE 4.x,5.x,6.x用(確認済み)
//
//  http://hp.vector.co.jp/authors/VA014069/
//  Sakamoto
//

module rom (
    dinp,
    wren,
    address,
    clk,
    enable,
    dout);

    input   [7:0]  dinp;
    input     wren;
    input   [8:0]  address;
    input     clk;
    input     enable;
    output  [7:0]  dout;


//  RAMB4_Sn プリミティブを使います
        RAMB4_S8    RAMB_EXAMPLE (
            .DO(dout),
            .ADDR(address),
            .DI(dinp),
            .EN(enable),
            .CLK(clk),
            .WE(wren),
            .RST(1'b0)
        );

//  ROMの内容を下記に書きます
//  (512アドレスx8bit幅=4096bits)
//
//synthesis attribute INIT_00 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INIT_01 of RAMB_EXAMPLE is "3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120"
//synthesis attribute INIT_02 of RAMB_EXAMPLE is "5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140"
//synthesis attribute INIT_03 of RAMB_EXAMPLE is "7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160"
//synthesis attribute INIT_04 of RAMB_EXAMPLE is "9F9E9D9C9B9A999897969594939291908F8E8D8C8B8A89888786858483828180"
//synthesis attribute INIT_05 of RAMB_EXAMPLE is "BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A0"
//synthesis attribute INIT_06 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_07 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_08 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_09 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0A of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0B of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0C of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0D of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0E of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0F of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"

endmodule

・ "tf_rom.tf"で保存

//
//  XILINX,Spartan-2 Block Select RAM
//  BLOCK-RAMをROMとして使う方法
//
//  ModelSimシミュレーション用
//
//  http://hp.vector.co.jp/authors/VA014069/
//  Sakamoto
//

`timescale 1ns/100ps

module tb();

parameter   P_CLOCK_FREQ    = 1000.0/50.000;    //  50.000MHz

// Inputs
    reg [7:0] dinp;
    reg wren;
    reg [8:0] address;
    reg clk;
    reg enable;


// Outputs
    wire [7:0] dout;


// Bidirs


// Instantiate the UUT
    rom d (
        .dinp(dinp),
        .wren(wren),
        .address(address),
        .clk(clk),
        .enable(enable),
        .dout(dout)
        );


// Initialize Inputs
        initial begin
            dinp = 0;
            wren = 0;
            address = 0;
            clk = 0;
            enable = 1;

            fork
                // Run the clock
                drive_clock;
                drive_adrs;
            join
        end

//  CLOCK DRIVE
task drive_clock;
    begin
        clk  = 0;
        forever begin
            #(P_CLOCK_FREQ/2) clk = ~clk;
        end
    end
endtask

//  ADRS DRIVE
task drive_adrs;
    begin
        address  = 0;
        forever begin
            #(P_CLOCK_FREQ) address = address + 1;
        end
    end
endtask

endmodule

・ FloorPlanで確認

・ ModelSimで動作確認

・ RAMB16_S9を使った場合(2048アドレスx8bit幅=16384bits)

・ Spartan-3 FPGA でのブロックRAM の使用(XAPP463)

・ RAMB16_Sn 16384-Bit Data Memory and 2048-Bit Parity Memory

Spartan-3
Virtex-II
Virtex-II Pro
等で使用できます。

・ "rom3.v"で保存

//
//  XILINX,Spartan-3 Block Select RAM
//  BLOCK-RAMをROMとして使う方法
//
//  ISE 6.x用(確認済み)
//
//  http://hp.vector.co.jp/authors/VA014069/
//  Sakamoto
//

module rom3 (
    dinp,
    dinpp,
    wren,
    address,
    clk,
    enable,
    dout,
    doutp);

    input   [7:0]  dinp;
    input     dinpp;
    input     wren;
    input   [10:0]  address;
    input     clk;
    input     enable;
    output  [7:0]  dout;
    output  doutp;


//  RAMB16_Sn プリミティブを使います
        RAMB16_S9   RAMB_EXAMPLE (
            .DO(dout),
            .DOP(doutp),
            .ADDR(address),
            .DI(dinp),
            .DIP(dinpp),
            .EN(enable),
            .CLK(clk),
            .WE(wren),
            .SSR(1'b0)
        );

//  ROMの内容を下記に書きます
//  (2048アドレスx8bit幅=16384bits)
//
//synthesis attribute INIT_00 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INIT_01 of RAMB_EXAMPLE is "3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120"
//synthesis attribute INIT_02 of RAMB_EXAMPLE is "5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140"
//synthesis attribute INIT_03 of RAMB_EXAMPLE is "7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160"
//synthesis attribute INIT_04 of RAMB_EXAMPLE is "9F9E9D9C9B9A999897969594939291908F8E8D8C8B8A89888786858483828180"
//synthesis attribute INIT_05 of RAMB_EXAMPLE is "BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A0"
//synthesis attribute INIT_06 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_07 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_08 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_09 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0A of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0B of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0C of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0D of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0E of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_0F of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_10 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INIT_11 of RAMB_EXAMPLE is "3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120"
//synthesis attribute INIT_12 of RAMB_EXAMPLE is "5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140"
//synthesis attribute INIT_13 of RAMB_EXAMPLE is "7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160"
//synthesis attribute INIT_14 of RAMB_EXAMPLE is "9F9E9D9C9B9A999897969594939291908F8E8D8C8B8A89888786858483828180"
//synthesis attribute INIT_15 of RAMB_EXAMPLE is "BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A0"
//synthesis attribute INIT_16 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_17 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_18 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_19 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1A of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1B of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1C of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1D of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1E of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_1F of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_20 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INIT_21 of RAMB_EXAMPLE is "3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120"
//synthesis attribute INIT_22 of RAMB_EXAMPLE is "5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140"
//synthesis attribute INIT_23 of RAMB_EXAMPLE is "7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160"
//synthesis attribute INIT_24 of RAMB_EXAMPLE is "9F9E9D9C9B9A999897969594939291908F8E8D8C8B8A89888786858483828180"
//synthesis attribute INIT_25 of RAMB_EXAMPLE is "BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A0"
//synthesis attribute INIT_26 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_27 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_28 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_29 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2A of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2B of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2C of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2D of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2E of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_2F of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_30 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INIT_31 of RAMB_EXAMPLE is "3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423222120"
//synthesis attribute INIT_32 of RAMB_EXAMPLE is "5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140"
//synthesis attribute INIT_33 of RAMB_EXAMPLE is "7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160"
//synthesis attribute INIT_34 of RAMB_EXAMPLE is "9F9E9D9C9B9A999897969594939291908F8E8D8C8B8A89888786858483828180"
//synthesis attribute INIT_35 of RAMB_EXAMPLE is "BFBEBDBCBBBAB9B8B7B6B5B4B3B2B1B0AFAEADACABAAA9A8A7A6A5A4A3A2A1A0"
//synthesis attribute INIT_36 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_37 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_38 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_39 of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3A of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3B of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3C of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3D of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3E of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"
//synthesis attribute INIT_3F of RAMB_EXAMPLE is "0000000000000000000000000000000000000000000000000000000000000000"

//  パリティ用(2048bits)
//synthesis attribute INITP_00 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_01 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_02 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_03 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_04 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_05 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_06 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"
//synthesis attribute INITP_07 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100"

endmodule

・ "tf_rom3.tf"で保存

//
//  XILINX,Spartan-3 Block Select RAM
//  BLOCK-RAMをROMとして使う方法
//
//  ModelSimシミュレーション用
//
//  http://hp.vector.co.jp/authors/VA014069/
//  Sakamoto
//

`timescale 1ns/100ps

module tb3();

parameter   P_CLOCK_FREQ    = 1000.0/50.000;    //  50.000MHz

// Inputs
    reg [7:0] dinp;
    reg dinpp;
    reg wren;
    reg [10:0] address;
    reg clk;
    reg enable;


// Outputs
    wire [7:0] dout;
    wire doutp;


// Bidirs


// Instantiate the UUT
    rom3 d (
        .dinp(dinp),
        .dinpp(dinpp),
        .wren(wren),
        .address(address),
        .clk(clk),
        .enable(enable),
        .dout(dout),
        .doutp(doutp)
        );


// Initialize Inputs
        initial begin
            dinp = 0;
            dinpp = 0;
            wren = 0;
            address = 0;
            clk = 0;
            enable = 1;

            fork
                // Run the clock
                drive_clock;
                drive_adrs;
            join
        end

//  CLOCK DRIVE
task drive_clock;
    begin
        clk  = 0;
        forever begin
            #(P_CLOCK_FREQ/2) clk = ~clk;
        end
    end
endtask

//  ADRS DRIVE
task drive_adrs;
    begin
        address  = 0;
        forever begin
            #(P_CLOCK_FREQ) address = address + 1;
        end
    end
endtask

endmodule

・ FloorPlanで確認

・ ModelSimで動作確認

Tags: [FPGA], [電子工作]

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